ID | 26037 | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Package Name | verilator | ||||||||||||||||
Links | Fedora Package Sources | Fedora Official Koji Buildsystem | Rocks RISC-V Koji Buildsystem | Fedora RISC-V GitHub | Old Koji Buildsystem | ||||||||||||||||
Version | 5.024 | ||||||||||||||||
Release | 2.fc41 | ||||||||||||||||
Epoch | Draft | False | |||||||||||||||
Source | git+https://src.fedoraproject.org/rpms/verilator.git#978de543b6b7ed7db4b89a91f0cac05f145d72b3 | ||||||||||||||||
Summary | A fast simulator for synthesizable Verilog | ||||||||||||||||
Description | Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. | ||||||||||||||||
Built by | kojiadmin | ||||||||||||||||
State | complete | ||||||||||||||||
Volume | DEFAULT | ||||||||||||||||
Started | Tue, 07 May 2024 05:27:49 CST | ||||||||||||||||
Completed | Tue, 07 May 2024 07:27:57 CST | ||||||||||||||||
Task | build (f41, /rpms/verilator.git:978de543b6b7ed7db4b89a91f0cac05f145d72b3) | ||||||||||||||||
Extra | {'source': {'original_url': 'git+https://src.fedoraproject.org/rpms/verilator.git#978de543b6b7ed7db4b89a91f0cac05f145d72b3'}} | ||||||||||||||||
Tags |
|
||||||||||||||||
RPMs |
|
||||||||||||||||
Logs |
|
||||||||||||||||
Changelog | * Fri Apr 05 2024 Nolan Poe <npgo22@gmail.com> - 5.024-2 - RPMAUTOSPEC: unresolvable merge |