verilator-5.024-2.fc40 | Build Info | ISCAS openkoji system

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Information for build verilator-5.024-2.fc40

45593

Package Name

Links

Fedora Package Sources | Fedora Official Koji Buildsystem | Rocks RISC-V Koji Buildsystem | Fedora RISC-V GitHub | Old Koji Buildsystem

Version

5.024

Release

2.fc40

Epoch

Draft

False

Source

git+https://src.fedoraproject.org/rpms/verilator.git#978de543b6b7ed7db4b89a91f0cac05f145d72b3

Summary

A fast simulator for synthesizable Verilog

Description

Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.

Built by

kojiadmin

State

complete

Volume

DEFAULT

Started

Sun, 05 May 2024 00:02:57 CST

Completed

Sun, 05 May 2024 02:19:37 CST

Task

build (f40, /rpms/verilator.git:978de543b6b7ed7db4b89a91f0cac05f145d72b3)

Extra

{'source': {'original_url': 'git+https://src.fedoraproject.org/rpms/verilator.git#978de543b6b7ed7db4b89a91f0cac05f145d72b3'}}

Tags

f40

RPMs

src
	verilator-5.024-2.fc40.src.rpm (info) (download)
noarch
	verilator-doc-5.024-2.fc40.noarch.rpm (info) (download)
riscv64
	verilator-5.024-2.fc40.riscv64.rpm (info) (download)
	verilator-devel-5.024-2.fc40.riscv64.rpm (info) (download)
	verilator-debuginfo-5.024-2.fc40.riscv64.rpm (info) (download)
	verilator-debugsource-5.024-2.fc40.riscv64.rpm (info) (download)

Logs

riscv64
	hw_info.log
	installed_pkgs.log
	state.log
	root.log
	build.log
	mock_output.log
	noarch_rpmdiff.json

Changelog

* Fri Apr 05 2024 Nolan Poe <npgo22@gmail.com> - 5.024-2 - RPMAUTOSPEC: unresolvable merge