Information for build verilator-5.026-2.fc41
| ID | 92072 | ||||||||||||||||
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| Package Name | verilator | ||||||||||||||||
| Links | Fedora Package Sources | Fedora Official Koji Buildsystem | Rocks RISC-V Koji Buildsystem | Fedora RISC-V GitHub | Old Koji Buildsystem | ||||||||||||||||
| Version | 5.026 | ||||||||||||||||
| Release | 2.fc41 | ||||||||||||||||
| Epoch | Draft | False | |||||||||||||||
| Source | git+https://src.fedoraproject.org/rpms/verilator.git#b41054f222af47f93c451727da5a0b94c7983fe6 | ||||||||||||||||
| Summary | A fast simulator for synthesizable Verilog | ||||||||||||||||
| Description | Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. | ||||||||||||||||
| Built by | kojiadmin | ||||||||||||||||
| State | complete | ||||||||||||||||
| Volume | DEFAULT | ||||||||||||||||
| Started | Mon, 07 Oct 2024 07:14:35 CST | ||||||||||||||||
| Completed | Mon, 07 Oct 2024 09:46:06 CST | ||||||||||||||||
| Task | build (f41-build-side-1, /rpms/verilator.git:b41054f222af47f93c451727da5a0b94c7983fe6) | ||||||||||||||||
| Extra | {'source': {'original_url': 'git+https://src.fedoraproject.org/rpms/verilator.git#b41054f222af47f93c451727da5a0b94c7983fe6'}} | ||||||||||||||||
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| Changelog | * Sat Jul 20 2024 Fedora Release Engineering <releng@fedoraproject.org> - 5.026-2 - Rebuilt for https://fedoraproject.org/wiki/Fedora_41_Mass_Rebuild * Mon Jul 15 2024 Nolan Poe <npgo22@gmail.com> - 5.026-1 - Update to Verilator 5.026 * Fri Apr 05 2024 Nolan Poe <npgo22@gmail.com> - 5.024-2 - RPMAUTOSPEC: unresolvable merge |