Information for RPM vhd2vl-2.5-18.fc40.src.rpm
| ID | 166534 | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| Build | vhd2vl-2.5-18.fc40 | ||||||||
| Name | vhd2vl | ||||||||
| Version | 2.5 | ||||||||
| Release | 18.fc40 | ||||||||
| Epoch | |||||||||
| Arch | src | ||||||||
| Draft | False | ||||||||
| Summary | VHDL to Verilog translator | ||||||||
| Description | vhd2vl is a VHDL to Verilog translation program. It targets the translation of synthetisable RTL. While far from complete it supports a useful subset of VHDL, sufficient for complex designs. | ||||||||
| Build Time | 2024-05-04 16:16:43 GMT | ||||||||
| Size | 61.83 KB | ||||||||
| 1a20dc76269b359d715058d26bc5212d | |||||||||
| License | GPLv2+ | ||||||||
| Buildroot | f40-build-135945-7241 | ||||||||
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| Obsoletes | No Obsoletes | ||||||||
| Conflicts | No Conflicts | ||||||||
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| Recommends | No Recommends | ||||||||
| Suggests | No Suggests | ||||||||
| Supplements | No Supplements | ||||||||
| Enhances | No Enhances | ||||||||
| Files |
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| Component of | No Buildroots | ||||||||
