Information for RPM vhd2vl-2.5-20.fc41.src.rpm
| ID | 374317 | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| Build | vhd2vl-2.5-20.fc41 | ||||||||
| Name | vhd2vl | ||||||||
| Version | 2.5 | ||||||||
| Release | 20.fc41 | ||||||||
| Epoch | |||||||||
| Arch | src | ||||||||
| Draft | False | ||||||||
| Summary | VHDL to Verilog translator | ||||||||
| Description | vhd2vl is a VHDL to Verilog translation program. It targets the translation of synthetisable RTL. While far from complete it supports a useful subset of VHDL, sufficient for complex designs. | ||||||||
| Build Time | 2024-09-29 07:49:23 GMT | ||||||||
| Size | 61.51 KB | ||||||||
| f46328aa035ec34733255d1bc4ddb006 | |||||||||
| License | GPL-2.0-or-later | ||||||||
| Buildroot | f41-build-side-1-2762707-31863 | ||||||||
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| Obsoletes | No Obsoletes | ||||||||
| Conflicts | No Conflicts | ||||||||
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| Recommends | No Recommends | ||||||||
| Suggests | No Suggests | ||||||||
| Supplements | No Supplements | ||||||||
| Enhances | No Enhances | ||||||||
| Files |
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| Component of | No Buildroots | ||||||||
